This is NeXT-and-3rd-party-memory. in view mode; [Up]
Date: Sun 29-Oct-1989 18:46:20 From: Unknown Subject: NeXT and 3'rd party memory. To all those wishing to upgrade their NeXT's memory without paying extraordinary prices. I looked into this matter a while back and these are the results (please forgive any inaccuracies): 1) The NeXT is fairly kind about memory. Pretty much any SIMM module will work provided that you use the "standard" configuration(s). As far as I know this is 4 MegaBytes or 4 modules at a time. For example, 4 1-MegaByte Simms will bring your cube from 8MB to 12MB. Also, 1 4-MegaByte Simm will do the same (these are rare and VERY expensive). If you have old Mac memory lying about (the 256K variety) you can put these to good use, 4 256K-Simms will give you an extra 1 MB (wow!). Naturally 8 1-MB SIMMs or 2 4-MB SIMMs will top your cube off at 16MB. The basic rule to remember is at least 4 boards or 4 MB's in a single bank (a "bank" being 4 slots usually). Being cheap and using say 2 1-MB SIMMs (to get 10MB) will not work. Rumor has it that other configurations are possible by changing some system register via the system monitor (I don't mean the display monitor, I mean the display you get when you do a "<command> <Alt> ~"). I think it's something in "scr2" (clues anyone?). 2) What kind of SIMMs? You need at least 256K 1x8 100ns SIMMs. At present the NeXT comes with at least eight 1MB 1x8 100ns page mode SIMMs. That is, each SIMM is 1MB, no parity, page mode, 100 nanoseconds access time. You can use 1x9 (parity), nibble mode, less than 100ns memory (or any permutation of such). These also can be mixed as along as they follow the (a) configuration. I use two 1x9 1MB 80ns SIMMs and two 1x8ns 1MB 80ns SIMMs in a single bank and things are just fine. 3) What is the difference between the various SIMMs? First is size, either 256k, 1MB, 4MB (are the standard values) These are self evident. Second is parity, 1x8 (read "1 by 8"), 1x9, 256x9 etc. This first digit refers to how the memory on each chip is accessed and the second is the number of chips. Usually the computer stores data as 8-bi t characters, one bit per chip in k levels (where k=256, 1MB, etc.); if a 9'th chip is present, it is used for parity (often used to insure the integrity of data). At present the NeXT does not use parity. Lastly the mysterious question or "page" vs "nibble" mode memory. You may have heard these terms in reference to "virtual memory" or software memory moves (i.e. copying one block of memory to another). For hardware memory this refers to how the data in the chip can be accessed. For "nibble" memory data can be accessed one "byte" at a time. That is, the processor (or memory management unit (MMU)) sets an address of a particular memory location and the chip outputs the data at that address (the time interval between giving the chip an address and outputing data is the "access time", e.g. 100ns, 80ns etc.). In "page" style memory, the chip is given a starting address and a block size. The chip will then dump data from(starting address) to (starting address+block size). These days more than 95% of the SIMMs are page mode, so you probably won't ever see any nibble mode SIMMs However, at present the 4MB SIMMs are nibble mode. Regardless of this, the NeXT uses a MMU to negotiate usage, so you can use both page and nibble mode memory. 4) What should you buy and where? I recommend 1x8 1MB 100ns page mode SIMMs from Technology Works in Austin Texas. They go for around $96 each (remember you need at least 4). They are a very good company, offering a lifetime warranty and excellent shipping service. They will accept university P.O.'s and credit cards or whatever. I was told that if I could gather enough simultaneous orders that there would be a substantial discount. If you're interested in doing this, send me your name, address, and how much you want to order. After a reasonable amount of time I will find out how much of a discount we can get and we'll take it from there. Here is their address: Technology Works 4030 Braker Ln. West, Suite 350 Austin, TX 78759 Voice: 512-794-8533 Fax: 512-794-8520 6) **** WARNING **** If it is true that NeXT will be upgrading soon to a 50mhz 68040 the present memory may be too slow (probably not though). I'm sure NeXT will not replace your 3'rd party memory. However, if this is the case I'm guessing the resale value of 100ns 1MB SIMMs will be at least %70 of what you will pay now until next year. Besides, it's not that expensive compared to what you might pay NeXT for the extra memory. Corrections, comments, flames, sign-up's for discount to: Reply's to: dnp@math.ucla.edu In real life: Dan Port >From: eps@toaster.SFSU.EDU (Eric P. Scott)
Date: Sun 30-Oct-1989 16:12:04 From: Unknown Subject: Re: NeXT and 3'rd party memory. In article <1945@sunset.MATH.UCLA.EDU> dnp@MIT.UCLA.EDU () writes: > 6) **** WARNING **** > If it is true that NeXT will be upgrading soon to a 50mhz 68040 the present > memory may be too slow (probably not though). Does anybody know if this is true? If so, any details on what it means to upgrade? Cost? etc. ? Daniel Mark Gessel
Date: Sun 31-Oct-1989 07:47:49 From: Unknown Subject: Re: NeXT and 3'rd party memory. In article <1945@sunset.MATH.UCLA.EDU> dnp@MIT.UCLA.EDU () writes: > ... Lastly the > mysterious question or "page" vs "nibble" mode memory. You may have heard > these terms in reference to "virtual memory" or software memory moves > (i.e. copying one block of memory to another). For hardware memory > this refers to how the data in the chip can be accessed. For "nibble" > ... The descriptions of page-mode and nibble-mode access which followed were incorrect. Page-mode and nibble-mode 1Mx1 DRAMs support normal accesses, i.e row addr, RAS, column addr, CAS then read or write. A DRAM which also supports Page-mode can speed up access to bits located at the same row address, because you can hold RAS low, and just put out a column address and assert CAS. Nibble-mode speeds up access to sequential bits by allowing you to hold RAS low, and just assert CAS to get out the next bit. Row A9 and column A9 supply the two bits for the start of the sequence, and the sequence goes 00->01->10->11->00 ... The sequence can start at any point and wraps around as long as RAS is held low. -Jonathan -Jonathan >From: ramsdell@linus.UUCP (John D. Ramsdell)
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